The present invention relates generally to photolithography methods and systems, and more specifically to improved techniques for determining focus error.
Integrated circuits are made by photolithographic processes, which use photolithographic masks and an associated light or radiation source to project a circuit image onto a wafer. Referring to FIG. 1, for example, a simplified diagram of a lithography system 2 is shown. By way of example, the lithography system may correspond to a stepper or scanning system. The lithography system 1 typically includes a light or radiation source 3 and a first set of optics 4 that illuminate a mask 5 having a circuit pattern 6 disposed thereon. In order to form the circuit pattern, the mask 6 may include opaque portions and/or transmissive portions. As is generally well known, the opaque portions block the light from passing through the mask 6 while the transmissive portions allow the light to pass therethrough. In some cases, the transmissive portions may constitute phase shifted areas. Phase shifted areas tend to alter the phase of the light or radiation passing through the mask. The lithography system 2 also includes a second set of optics 7 that pick up the transmitted light or radiation and focuses (or images) it onto a surface 9 of a semiconductor wafer 8 thus writing the pattern of the mask 6 onto the surface 9 of the semiconductor wafer 8. In most cases, the semiconductor wafer 8 includes a layer of photoresist that when exposed to the patterned light or radiation forms the pattern of the mask onto the wafer.
One problem that has been encountered during lithographic processes is the misfocus found between the surface of the wafer being patterned on and the ideal focus plane. Referring back to FIG. 1, the light or radiation follows an optical path that corresponds to the Z axis. The first and second set of optics as well as the mask and the wafer are thus positioned orthogonal to the optical path in different X&Y planes. With this in mind, the second set of optics generally focuses the light on a specific X&Y plane (not shown) positioned along the Z axis. This plane is generally referred to as the ideal focus plane. When the system is in focus, the ideal focus plane generally coincides with the surface of the wafer. When the system is out of focus, the ideal focus plane is offset relative to the surface of the wafer. That is, there is Z axis displacement between the ideal focus plane and the surface of the wafer being written on and thus there is misfocus. As should be appreciated, misfocus generally has a sign and magnitude corresponding to the Z axis displacement. The sign corresponds to the direction of the displacement (e.g., positive or negative), and the magnitude corresponds to the amount of displacement (e.g., the actual distance between planes). The displacement may be caused by many factors. For example, the second set of optics and/or the wafer may be mis-aligned (e.g., tilted) or they may be positioned in the wrong plane along the Z axis.
Unfortunately, misfocus may adversely effect the printed pattern on the wafer. For example, misfocus may cause increases or decreases in the width of the lines printed on the wafer, i.e., linewidth is a function of focus. The linewidth generally determines the speed and the timing across the circuit and thus misfocus may cause one portion of the chip to run faster or slower than another portion of the chip. In most cases, the chip is clocked to the slowest portion thereby reducing the selling price of the chip. In addition, misfocus may cause open or shorted circuits such that the chip must be discarded or reworked. Presently, focus is determined by exposing a pattern through a range of focus settings, and then inspecting the resultant patterns for the best looking images or by using an aerial image monitor to determine the spatial location of the best focus.
In view of the foregoing, there is a desire for improved techniques for determining focus error, as for example, the direction (i.e., the positive or negative Z-axis translation of the wafer) and the magnitude (i.e., offset displacement) of misfocus.